1. Field of the Invention
The present invention relates to a phase synchronous circuit, and more particularly to a phase synchronous circuit for selecting a signal from multiphase clock signals and outputting a signal synchronized in phase with a reference signal.
2. Description of Related Art
Most electronic apparatuses use circuits generating signals synchronized with reference signals. For example, in computers, a circuit for selecting and outputting a clock signal with a prescribed frequency from a generator according to a reference signal is used to generate a clock signal supplied to a CPU or chip set. PLL (Phase-Locked Loop) or DLL (Delay-Locked Loop) method have been suggested as methods for phase synchronization with a reference signal, in particular as methods for phase synchronization with a periodic reference signal.
A phase synchronous circuit according to the related technique is disclosed, for example, in Japanese Patent Application Laid-open No. 2001-351381. This document discloses a phase synchronous circuit for synchronization with a reference signal serving as a periodic signal. FIG. 13 is a circuit diagram illustrating a general configuration of the phase synchronous circuit according to the related technique. The phase synchronous circuit shown in FIG. 13 is a DLL feedback circuit and puts out an output signal DOUT in phase with an EXCLK. Further, the phase synchronous circuit comprises a phase comparator 710, a delay control circuit 720, a variable delay circuit 730, and a replica delay circuit 740.
The operation of the phase synchronous circuit will be explained below. The phase comparator 710 compares the phases of a reference clock signal EXCLK and a recovery clock signal RCLK and outputs a signal corresponding to the comparison result to the delay control circuit 720. The delay control circuit 720 controls the delay of the variable delay circuit 730 according to the comparison results of the phase comparator 710 so that the phases thereof coincide.
The output from the variable delay circuit 730 is outputted as an output signal DOUT to the outside via a data output control circuit 750. A delay is generated in the data output control circuit 750 between the output timing of the variable delay circuit 730 and the output timing of the output signal DOUT. A replica delay circuit 740 is connected between the data output control circuit 750 and phase comparator 710 such that the phases of the reference signal EXCLK and output signal DOUT coincide.
The delay time of the replica delay circuit 740 is equal to the delay time in the data output control circuit 750 and the phases of the reference signal EXCLK and output signal DOUT can coincide. Typically, the replica delay circuit 740 has a circuit configuration identical to that of data output control circuit 750 in order to reduce the delay error relative to the data output control circuit 750 caused by manufacturing variations or usage conditions.
FIG. 14 is a timing chart illustrating changes with time of the reference clock signal EXCLK, replica clock signal RCLK, output signal CLK2 of the variable delay circuit 730, and output signal DOUT. As shown in FIG. 14, because the phases of EXCLK and RCLK coincide, CLK2 corresponding to the input signal of the replica delay circuit 740 is a leading clock that leads in phase the EXCLK by the delay time of the replica delay circuit 740. Further, as described hereinabove, the delay time of the data output control circuit 750 is equal to the delay time of the replica delay circuit 740. Therefore, the phase of DOUT generated by the data output control circuit 750 from CLK2 is synchronized with the phase of EXCLK.
In the phase synchronization approach of circuits illustrated by FIG. 13, the internal delay is cancelled by matching the phases of the signal RCLK after the replica delay and the input reference signal EXCLK and driving the output circuit by using the signal CLK2 before the replica delay as a trigger.
On the other hand, Japanese Patent Application Laid-open No. 2000-315944 suggests a synchronized clock signal generator for generating a synchronized clock signal by generating a plurality of clock signals with different phases and selecting a clock signal with the minimum shift in timing with respect to the reference signal. Such a synchronized clock signal generator is used for generating synchronization signals for printers. In order to generate a plurality of clock signals with different phases, first, the generator generates a clock signal at a regular bit rate frequency. This clock signal is delayed by multiple stage buffers, and each buffer outputs a delay signal with different delay time. As a result, a plurality of clock signals with different phases are generated.
Further, the output signal of a beam detector is inputted as a reference signal. The timing of the reference signal and the output timing of each buffer are compared and a clock signal closest to the timing of the reference signal is selected. The selected clock signal is outputted as a synchronized clock signal synchronized with the reference signal. As a result, a synchronized clock signal generation apparatus using a generator with a comparatively low frequency can be obtained and circuit design can be facilitated.
The DLL circuit disclosed in Japanese Patent Application Laid-open No. 2001-351381 can generate a signal that is synchronized in phase with a periodic reference signal. However, when the reference signal is a nonperiodic signal and inputted randomly, phase synchronization with a feedback circuit such as DLL cannot be conducted. On the other hand, with the synchronized clock signal generation apparatus disclosed in Japanese Patent Application Laid-open No. 2000-315944, a signal synchronized in phase with a reference signal can be generated even when the reference signal is a nonperiodic signal by selecting a clock signal from multiphase clock signals with different phases correspondingly to the reference signal.
However, the delay in internal circuits in phase synchronization between a reference signal and multiphase clock signals has not yet been studied. For this reason, when a delay caused by the internal circuits is produced with respect to the reference signal or multiphase clock signal, an output signal synchronized with the reference signal cannot be generated. Therefore, phase synchronous circuits using multiphase clock signals are required to have a configuration which compensates for the internal delay with a necessary accuracy. Furthermore, the reduction of circuit area and power consumption is constantly required for semiconductor circuit devices. Therefore, it is desirable that the internal delay be compensated for with an efficient circuit configuration.